This application claims the priority of Korean Patent Application No. 2002-61487, filed 9 Oct. 2002 in the Korean Intellectual Property Office (KIPO), which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a data bus system for a micro controller, and more particularly, to a data bus system for a micro controller having a plurality of sub data buses.
2. Description of the Related Art
In general, a microprocessor is one of various types of central processing units (CPUs), which is a semiconductor device in which a CPU of a computer is integrated on a single integrated circuit. A micro controller refers to a single chip with the built-in CPU, storage unit having a certain capacity, and input/output (I/O) control circuit. In the micro controller, movement of data within the micro controller is made via a data bus, and a system relating to the movement of data via the data bus is called a data bus system.
FIG. 1 is a block diagram of an example of conventional data bus systems for a micro controller. Referring to FIG. 1, the data bus system includes a data bus 102 and an address bus 104 which are connected to an I/O unit 112, a CPU 114, a memory unit 116, and a peripheral circuitry 118. Therefore, via the data bus 102, data is moved between the CPU 114 and the memory unit 116, between the CPU 114 and the peripheral circuitry 18, or between the CPU 114 and the I/O unit 112. During the movement of data, only one block related to the movement of data is open, thereby preventing the other blocks from interrupting the exchange of data.
However, the conventional data bus system is disadvantageous in that one data bus 102 is shared by the I/O unit 112, the CPU 114, the memory unit 116, and the peripheral circuitry 118. In this case, a greater amount of load capacitance is weighed on the data bus 102. Moreover, as the number of peripheral circuits installed in a micro controller is increased, the amount of data input to and output from the peripheral circuits are increased, thereby increasing loads weighed on the data bus 102. An increase in the loads on the data bus 102 results in a reduction in the operational speed of a data bus system and an increase in power consumption therein.